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1 data sheet acquired from harris semiconductor schs141h features hysteresis on clock inputs for improved noise immunity and increased input rise and fall times asynchronous set and reset complementary outputs buffered inputs typical f max = 60mhz at v cc = 5v, c l = 15pf, t a = 25 o c fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads wide operating temperature range . . . -55 o c to 125 o c balanced propagation delay and transition times signi?ant power reduction compared to lsttl logic ics hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 a at v ol , v oh pinout cd54hc112, cd54hct112 (cerdip) cd74hc112 (pdip, soic, sop, tssop) cd74hct112 (pdip) top view description the ?c112 and ?ct112 utilize silicon-gate cmos technology to achieve operating speeds equivalent to lsttl parts. they exhibit the low power consumption of standard cmos integrated circuits, together with the ability to drive 10 lsttl loads. these ?p-?ps have independent j, k, set, reset, and clock inputs and q and q outputs. they change state on the negative-going transition of the clock pulse. set and reset are accomplished asynchronously by low-level inputs. the hct logic family is functionally as well as pin- compatible with the standard ls logic family. . 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 1cp 1k 1j 1s 1q 1q gnd 2q v cc 2r 2cp 2k 2j 2s 2q 1r ordering information part number temp. range ( o c) package cd54hc112f3a -55 to 125 16 ld cerdip cd54hct112f3a -55 to 125 16 ld cerdip cd74hc112e -55 to 125 16 ld pdip cd74hc112mt -55 to 125 16 ld soic cd74hc112m96 -55 to 125 16 ld soic cd74hc112nsr -55 to 125 16 ld sop cd74hc112pw -55 to 125 16 ld tssop cd74hc112pwr -55 to 125 16 ld tssop cd74hc112pwt -55 to 125 16 ld tssop cd74hct112e -55 to 125 16 ld pdip note: when ordering, use the entire part number. the suf?es 96 and r denote tape and reel. the suf? t denotes a small-quantity reel of 250. caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright 2003, texas instruments incorporated cd54hc112, cd74hc112, cd54hct112, cd74hct112 dual j-k flip-flop with set and reset negative-edge trigger [ /title ( cd74 h c112 , c d74 h ct11 2 ) / sub- j ect ( dual j -k f lip- f lop w ith s et and r eset n ega- march 1998 - revised october 2003
2 functional diagram truth table inputs outputs s r cp j k q q lhxxxhl h l xxxlh l l x x x h (note 1) h (note 1) h h l l no change h h hlhl hh lhlh hh h h toggle h h h x x no change h= high level (steady state) l= low level (steady state) x= don? care = high-to-low transition note: 1. output states unpredictable if both s and r go high simultaneously after both being low at the same time. 1s 2s 2r 4 10 5 6 1q 1q 14 15 1r 2k 12 13 9 7 2q 2q 2cp f/f 1 f/f 2 gnd = 8 v cc = 16 2j 11 1k 2 1 1cp 1j 3 cd54hc112, cd74hc112, cd54hct112, cd74hct112
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc drain current, per output, i o for -0.5v < v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . . . . . 25ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc . . . . . . . . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range, t a . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time, t r , t f 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (max) package thermal impedance, ja (see note 2): e (pdip) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 o c/w ns (sop) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 o c/w d (soic) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 o c/w pw (tssop) package . . . . . . . . . . . . . . . . . . . . . . . . . 108 o c/w maximum junction temperature (hermetic package or die) . 175 o c maximum junction temperature (plastic package) . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 2. the package thermal impedance is calculated in accordance with jesd 51-7. dc electrical speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v 4.5 4.4 - - 4.4 - 4.4 - v 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads ---------v -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 4.5 - - 0.1 - 0.1 - 0.1 v 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads ---------v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 a cd54hc112, cd74hc112, cd54hct112, cd74hct112
4 quiescent device current i cc v cc or gnd 0 6 - - 4 - 40 - 80 a hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage cmos loads v oh v ih or v il -0.02 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc and gnd - 5.5 - 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 5.5 - - 4 - 40 - 80 a additional quiescent device current per input pin: 1 unit load ? i cc (note 3) v cc - 2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 a note: 3. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. dc electrical speci?ations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads 1s, 2s 0.5 1k, 2k 0.6 1r, 2r 0.65 1j, 2j, 1cp, 2cp 1 note: unit load is ? i cc limit speci?d in dc electrical speci?a- tions table, e.g., 360 a max at 25 o c. prerequisite for switching speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types pulse width cp t w - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns cd54hc112, cd74hc112, cd54hct112, cd74hct112
5 pulse width r, st w - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns setup time j, k, to cp t su - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns hold time j, k, to cp t h -20--0-0-ns 4.5 0 - - 0 - 0 - ns 60--0-0-ns removal time r to cp, s to cp t rem - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns cp frequency f max - 2 6 - - 5 - 4 - mhz 4.5 30 - - 25 - 20 - mhz 6 35 - - 29 - 23 - mhz hct types pulse width cp t su - 4.5 16 - - 20 - 24 - ns pulse width r, st w - 4.5 18 - - 23 - 27 - ns setup time j, k, to cp t h - 4.5 16 - - 20 - 24 - ns hold time j, k, to cp t rem - 4.5 3 - - 3 - 3 - ns removal time r to cp, s to cp t w - 4.5 20 - - 25 - 30 - ns cp frequency f max - 4.5 30 - - 25 - 20 - mhz switching speci?ations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types propagation delay, cp to q, q t plh , t phl c l = 50pf 2 - - 175 - 220 - 265 ns c l = 50pf 4.5 - - 35 - 44 - 53 ns c l = 15pf 5 - 14 - ----ns c l = 50pf 6 - - 30 - 37 - 45 ns propagation delay, s to q, q t plh , t phl c l = 50pf 2 - - 155 - 195 - 235 ns c l = 50pf 4.5 - - 31 - 39 - 47 ns c l = 15pf 5 - 13 - ----ns c l = 50pf 6 - - 26 - 33 - 40 ns propagation delay, r to q, q t plh , t phl c l = 50pf 2 - - 180 - 225 - 270 ns c l = 50pf 4.5 - - 36 - 45 - 54 ns c l = 15pf 5 - 15 - ----ns c l = 50pf 6 - - 31 - 38 - 46 ns prerequisite for switching speci?ations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max cd54hc112, cd74hc112, cd54hct112, cd74hct112
6 output transition time t tlh , t thl c l = 50pf 2 - - 75 - 95 - 110 ns c l = 50pf 4.5 - - 15 - 19 - 22 ns c l = 50pf 6 - - 13 - 16 - 19 ns input capacitance c i - - - - 10 - 10 - 10 pf cp frequency f max c l = 15pf 5 - 60 - ----mhz power dissipation capacitance (notes 4, 5) c pd - 5-12-----pf hct types propagation delay, cp to q, q t plh , t phl c l = 50pf 4.5 - - 35 - 44 - 53 ns c l = 15pf 5 - 14 - ----ns propagation delay, s to q, q t plh , t phl c l = 50pf 4.5 - - 32 - 40 - 48 ns c l = 15pf 5 - 13 - ----ns propagation delay, r to q, q t plh , t phl c l = 50pf 4.5 - - 37 - 46 - 56 ns c l = 15pf 5 - 14 - ----ns output transition time t tlh , t thl c l = 50pf 4.5 - - 15 - 19 - 22 ns input capacitance c i - - - - 10 - 10 - 10 pf cp frequency f max cl = 15pf 5 - 60 - ----mhz power dissipation capacitance (notes 4, 5) c pd - 5-20-----pf notes: 4. c pd is used to determine the dynamic power consumption, per flip-flop. 5. p d = c pd v cc 2 f i + c l f o where f i = input frequency, f o = output frequency, c l = output load capacitance, v cc = supply voltage. switching speci?ations input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max test circuits and waveforms note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 1. hc clock pulse rise and fall times and pulse width note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 2. hct clock pulse rise and fall times and pulse width clock 90% 50% 10% gnd v cc t r c l t f c l 50% 50% t wl t wh 10% t wl + t wh = f cl i clock 2.7v 1.3v 0.3v gnd 3v t r c l = 6ns t f c l = 6ns 1.3v 1.3v t wl t wh 0.3v t wl + t wh = fc l i cd54hc112, cd74hc112, cd54hct112, cd74hct112
7 figure 3. hc and hcu transition times and propaga- tion delay times, combination logic figure 4. hct transition times and propagation delay times, combination logic figure 5. hc setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits figure 6. hct setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits test circuits and waveforms (continued) t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90% t r c l t f c l gnd v cc gnd v cc 50% 90% 10% gnd clock input data input output set, reset or preset v cc 50% 50% 90% 10% 50% 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) t h(h) t r c l t f c l gnd 3v gnd 3v 1.3v 2.7v 0.3v gnd clock input data input output set, reset or preset 3v 1.3v 1.3v 1.3v 90% 10% 1.3v 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) 1.3v t h(h) 1.3v cd54hc112, cd74hc112, cd54hct112, cd74hct112
package option addendum www.ti.com 10-jun-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples 5962-8970201ea active cdip j 16 1 tbd a42 n / a for pkg type -55 to 125 5962-8970201ea cd54hct112f3a cd54hc112f3a active cdip j 16 1 tbd a42 n / a for pkg type -55 to 125 8408801ea cd54hc112f3a cd54hct112f3a active cdip j 16 1 tbd a42 n / a for pkg type -55 to 125 5962-8970201ea cd54hct112f3a cd74hc112e active pdip n 16 25 pb-free (rohs) cu nipdau n / a for pkg type -55 to 125 cd74hc112e cd74hc112m96 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hc112m cd74hc112mt active soic d 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hc112m cd74hc112nsr active so ns 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hc112m cd74hc112pw active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hj112 cd74hc112pwr active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hj112 CD74HC112PWRE4 active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hj112 cd74hc112pwrg4 active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hj112 cd74hc112pwt active tssop pw 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hj112 cd74hct112e active pdip n 16 25 pb-free (rohs) cu nipdau n / a for pkg type -55 to 125 cd74hct112e cd74hct112ee4 active pdip n 16 25 pb-free (rohs) cu nipdau n / a for pkg type -55 to 125 cd74hct112e (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device.
package option addendum www.ti.com 10-jun-2014 addendum-page 2 (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of cd54hc112, cd54hct112, cd74hc112, cd74hct112 : ? catalog: cd74hc112 , cd74hct112 ? military: cd54hc112 , cd54hct112 note: qualified version definitions: ? catalog - ti's standard catalog product
package option addendum www.ti.com 10-jun-2014 addendum-page 3 ? military - qml certified for military and defense applications
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant cd74hc112m96 soic d 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 q1 cd74hc112nsr so ns 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 q1 cd74hc112pwr tssop pw 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 cd74hc112pwt tssop pw 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) cd74hc112m96 soic d 16 2500 333.2 345.9 28.6 cd74hc112nsr so ns 16 2000 367.0 367.0 38.0 cd74hc112pwr tssop pw 16 2000 367.0 367.0 35.0 cd74hc112pwt tssop pw 16 250 367.0 367.0 35.0 package materials information www.ti.com 14-jul-2012 pack materials-page 2

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